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low power, 24-bit sigma-delta adc with in- amp and embedded reference (6 channel) preliminary technical data AD7794 rev.pre 6/04. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features six differential analog inputs low noise programmable gain instrumentation-amp rms noise: 80 nv (gain = 64) bandgap reference with 5 ppm/ c drift typ power supply: 2.7 v to 5.25 v operation normal: 400 a typ power-down: 1 a max update rate: 4 hz to 500 hz simultaneous 50 hz/60 hz rejection internal clock oscillator reference detect programmable current sources (10 a/200 a/1 ma) on-chip bias voltage generator 100 na burnout currents low side power switch independent interface power supply 24-lead tssop package interface 3-wire serial spi?, qspi?, microwire?, and dsp compatible schmitt trigger on sclk applications temperature measurement pressure measurement weigh scales general description the AD7794 is a low power, complete analog front end for low frequency measurement applications. it contains a low noise 24-bit -? adc with six differential inputs. the on-chip low noise instrumentation amplifier means that signals of small amplitude can be interfaced directly to the adc. the device contains a precision low noise, low drift internal reference for absolute measurements. an external reference can also be used if ratiometric measurements are required. other on-chip features include programmable excitation current sources and a bias voltage generator for temperature applica- tions along with 100 na burnout currents. for pressure and weighscale applications, a low-side power switch is available to power down the bridge between conversions to minimize the power consumption of the system. the device can be operated with the internal clock or, alternatively, an external clock can be used if synchronizing several devices. the output data rate from the part is software programmable and can be varied from 4 hz to 500 hz. the part operates with a power supply from 2.7 v to 5.25 v. it consumes a current of 450 ua maximum and is housed in a 24- lead tssop package. functional block diagram AD7794 serial interface and control logic internal clock cl k sigma delta adc ain1(+) ain1(-) ain5(+)/iout2 ain5(-)/iout1 mux in-amp refin1(+) refin1(-) bandgap reference gnd v dd gnd v dd psw reference detect ain2(+) ain2(-) ain6(+)/p1 ain6(-)/p2 ain3(+) ain3(-) ain4(+)/refin2(+) ain4(-)/refin2(-) v bias gnd gnd av dd dout/rdy din sclk cs dvdd temp sensor
AD7794 preliminary technical data rev.pre 6/04 | page 2 table of contents AD7794specifications.................................................................. 3 timing characteristics , .................................................................... 9 absolute maximum ratings.......................................................... 11 esd caution................................................................................ 11 pin configuration and function descriptions........................... 12 typical performance characteristics ........................................... 14 on-chip registers ........................................................................... 15 communications register (rs2, rs1, rs0 = 0, 0, 0) .............. 15 status register (rs2, rs1, rs0 = 0, 0, 0; power-on/reset = 0x88)............................................................................................. 16 mode register (rs2, rs1, rs0 = 0, 0, 1; power-on/reset = 0x000a)........................................................................................ 16 configuration register (rs2, rs1, rs0 = 0, 1, 0; power- on/reset = 0x0710) .................................................................... 18 data register (rs2, rs1, rs0 = 0, 1, 1; power-on/reset = 0x000000) .................................................................................... 20 id register (rs2, rs1, rs0 = 1, 0, 0; power-on/reset = 0xxf) ....................................................................................................... 20 io register (rs2, rs1, rs0 = 1, 0, 1; power-on/reset = 0x00) ....................................................................................................... 20 offset register (rs2, rs1, rs0 = 1, 1, 0; power-on/reset = 0x800000) .................................................................................... 21 full-scale register (rs2, rs1, rs0 = 1, 1, 1; power- on/reset = 0x5xxxx5) ................................................................ 21 adc circuit information.............................................................. 22 overview ..................................................................................... 22 noise performance ..................................................................... 22 digital interface .......................................................................... 23 single conversion mode ....................................................... 24 continuous conversion mode............................................. 24 continuous read mode ........................................................ 25 circuit description......................................................................... 26 analog input channel ............................................................... 26 bipolar/unipolar configuration .............................................. 26 data output coding .................................................................. 26 reference ..................................................................................... 26 v dd monitor ................................................................................ 27 grounding and layout .............................................................. 27 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history rev.pre, june 2004: initial version
preliminary technical data AD7794 rev.pre 6/04 | page 3 AD7794specifications 1 table 1. (av dd = 2.7 v to 5.25 v; dv dd = 2.7 v to 5.25 v; gnd = 0 v; all specifications t min to t max , unless otherwise noted.) parameter AD7794b unit test conditions/comments AD7794 (chop enabled) output update rate 4 hz min nom se ttling time = 2/output update rate 500 hz max nom no missing codes 2 24 bits min f adc 125 hz resolution (pk C pk) 16 bits p-p gain = 128, 16.6 hz update rate, v ref = 2.5 v 19 bits p-p gain = 1, 16.6 hz update rate, v ref = 2.5 v output noise and update rates see tables in adc description integral nonlinearity 15 ppm of fs r max 3.5 ppm typ. gain = 1 to 32 25 ppm of fsr max 5 ppm typ, gain = 64 or 128 offset error 3 3 v typ offset error drift vs. temperature 4 10 nv/c typ full-scale error 3, 5 10 v typ gain drift vs. temperature 4 0.5 ppm/c typ gain = 1 or 2 3 ppm/c typ gain = 4 to 128 power supply rejection 90 db min 100 db typ, ain = fs/2 analog inputs differential input voltage ranges refin/gain v nom refin = refin(+) C refin(C) or internal reference, gain = 1 to 128 absolute ain voltage limits 2 unbuffered mode gnd C 30 mv v min gain = 1 or 2 av dd + 30 mv v max buffered mode gnd + 100 mv v min gain = 1 or 2 av dd C 100 mv v max in-amp enabled gnd + 300 mv v min gain = 4 to 128 av dd C 1.1 v max common mode voltage 0.5 v min gain = 4 to 128 analog input current buffered mode or in-amp enabled average input current 2 200 pa max average input current drift 2 pa/c typ unbuffered mode gain = 1 or 2 average input current 400 na/v typ in put current varies with input voltage. average input current drift 50 pa/v/c typ 1 na max ain6(+) / ain6(-) normal mode rejection 2 internal clock @ 50 hz, 60 hz 70 db min 80 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 6 @ 50 hz 84 db min 90 db typ, 50 1 hz, fs[3:0] = 1001 6 @ 60 hz 90 db min 100 db typ, 60 1 hz, fs[3:0] = 1000 6 external clock @ 50 hz, 60 hz 80 db min 90 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 6 @ 50 hz 94 db min 100 db typ, 50 1 hz, fs[3:0] = 1001 6 @ 60 hz common mode rejection 90 db min 100 db typ, 60 1 hz, fs[3:0] = 1000 6 ain = +fs/2 @dc 90 db min fs[3:0] = 1010 6 @ 50 hz, 60 hz 2 100 db min 50 1 hz, 60 1 hz, fs[3:0] = 1010 6 @ 50 hz, 60 hz 2 100 db min 50 1 hz (fs[3:0] = 1001 6 ), 60 1 hz (fs[3:0] = 1000 6 )
AD7794 preliminary technical data rev.pre 6/04 | page 4 parameter AD7794b unit test conditions/comments reference input internal reference initial accuracy 1.17 0.01% v min/max internal reference drift 5 ppm/c typ 15 ppm/c max internal reference noise 2 v rms gain = 1, update rate = 16.6 hz. includes adc noise. external refin voltage 2.5 v nom refin = refin(+) C refin(C) reference voltage range 2 0.1 v min av dd v max absolute refin voltage limits 2 gnd C 30 mv v min av dd + 30 mv v max average reference input current 400 na/v typ average reference input current drift 0.03 na/v/c typ normal mode rejection 2 same as for analog inputs common mode rejection same as for analog inputs reference detect levels 0.3 v min noxref bit inactive if vref < 0.3 v 0.65 v max noxref bit active if vref > 0.65 v
preliminary technical data AD7794 rev.pre 6/04 | page 5 parameter AD7794b unit test conditions/comments AD7794 (chop disabled) output update rate 4 hz min nom se ttling time = 1/output update rate 500 hz max nom no missing codes 2 24 bits min f adc 125 hz resolution 15.5 bits p-p gain = 128, 16.6 hz update rate, v ref = 2.5 v 18.5 bits p-p gain = 1, 16.6 hz update rate, v ref = 2.5 v output noise and update rates see tables in adc description integral nonlinearity 15 ppm of fsr max 3.5 ppm of fsr typ. gain = 1 to 32 25 ppm of fsr max 5 ppm of fsr typ, gain = 64 or 128 offset error 3 200/gain v typ without calibration offset error drift vs. temperature 4 200/gain nv/c typ full-scale error 3, 5 10 v typ gain drift vs. temperature 4 0.5 ppm/c typ gain = 1 or 2 3 ppm/c typ gain = 4 to 128 power supply rejection 80 db min 100 db typ, ain = fs/2 analog inputs differential input voltage ranges refin/gain v nom refin = refin(+) C refin(C) or internal reference, gain = 1 to 128 absolute ain voltage limits 2 unbuffered mode gnd C 30 mv v min gain = 1 or 2 av dd + 30 mv v max buffered mode gnd + 100 mv v min gain = 1 or 2 av dd C 100 mv v max in-amp enabled gnd + 100 mv v min gain = 4 to 128 av dd C 1.1 v max common mode voltage 0.5 v min gain = 4 to 128 analog input current buffered mode or in-amp enabled average input current 2 200 pa max average input current drift 2 pa/c typ unbuffered mode gain = 1 or 2 average input current 400 na/v typ in put current varies with input voltage. average input current drift 50 pa/v/c typ 1 na max ain6(+) / ain6(-) normal mode rejection 2 internal clock @ 50 hz, 60 hz 60 db min 70 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 6 @ 50 hz 80 db min 90 db typ, 50 1 hz, fs[3:0] = 1001 6 @ 60 hz 90 db min 100 db typ, 60 1 hz, fs[3:0] = 1000 6 external clock @ 50 hz, 60 hz 60 db min 70 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 6 @ 50 hz 94 db min 100 db typ, 50 1 hz, fs[3:0] = 1001 6 @ 60 hz 90 db min 100 db typ, 60 1 hz, fs[3:0] = 1000 6 common mode rejection ain = +fs/2 @dc 80 db min fs[3:0] = 1010 6 @ 50 hz, 60 hz 2 80 db min 50 1 hz, 60 1 hz, fs[3:0] = 1010 6 @ 50 hz, 60 hz 2 80 db min 50 1 hz (fs[3:0] = 1001 6 ), 60 1 hz (fs[3:0] = 1000 6 ) reference input internal reference initial accuracy 1.17 0.01% v min/max internal reference drift 5 ppm/c typ 15 ppm/c max
AD7794 preliminary technical data rev.pre 6/04 | page 6 parameter AD7794b unit test conditions/comments internal reference noise 2 v rms gain = 1, update rate = 16.6 hz. includes adc noise. external refin voltage 2.5 v nom refin = refin(+) C refin(C) reference voltage range 2 0.1 v min v dd v max absolute refin voltage limits 2 gnd C 30 mv v min av dd + 30 mv v max average reference input current 400 na/v typ average reference input current drift 0.03 na/v/c typ normal mode rejection 2 same as for analog inputs common mode rejection same as for analog inputs reference detect levels 0.3 v min noxref bit inactive if vref < 0.3 v 0.65 v max noxref bit active if vref > 0.65 v
preliminary technical data AD7794 rev.pre 6/04 | page 7 parameter AD7794b unit test conditions/comments excitation current sources (iexc1 and iexc2) output current 10/200/1000 a nom initial tolerance at 25c 5 % typ drift 200 ppm/c typ initial current matching at 25c 1 % typ matching between iexc1 and exc2. v out = 0 v drift matching 20 ppm/c typ line regulation (v dd ) 2.1 ppm/v max av dd = 5 v 5%. typically 1.25 ppm/v load regulation 0.3 ppm/v typ output compliance av dd C 0.6 v max current sources programmed to 10 a or 200 a av dd C 1 v max current sources programmed to 1 ma gnd C 30 mv v min bias voltage generator v bias av dd /2 v nom v bias generator start-up time tbd ms/nf typ depe ndent on the capacitance connected to ain temperature sensor accuracy tbd c typ low side power switch r on 5 ? max av dd = 5 v 7 ? max av dd = 3 v allowable current 20 ma max continuous current digital outputs (p1 & p2) v oh , output high voltage 2 av dd C 0.6 v min av dd = 3 v, i source = 100 a v ol , output low voltage 2 0.4 v max av dd = 3 v, i sink = 100 a v oh , output high voltage 2 4 v min av dd = 5 v, i source = 200 a v ol , output low voltage 2 0.4 v max av dd = 5 v, i sink = 800 a floating-state leakage current 1 a max floating-state output ca pacitance 10 pf typ internal/external clock internal clock fequency 64 2% 64 2% duty cycle 50:50 50:50 drift 0.01 0.01 external clock frequency 64 64 duty cycle 45:55 45:55 logic inputs all inputs except sclk, din and clk 2 v inl , input low voltage 0.8 v max dv dd = 5 v 0.4 v max dv dd = 3 v v inh , input high voltage 2.0 v min dv dd = 3 v or 5 v sclk and din (schmitt-triggered input) 2 v t (+) 1.4/2 v min/v max dv dd = 5 v v t (C) 0.8/1.4 v min/v max dv dd = 5 v v t (+) C v t (C) 0.3/0.85 v min/v max dv dd = 5 v v t (+) 0.9/2 v min/v max dv dd = 3 v v t (C) 0.4/1.1 v min/v max dv dd = 3 v v t (+) - v t (C) 0.3/0.85 v min/v max dv dd = 3 v clk 2 v inl , input low voltage 0.8 v max dv dd = 5 v v inl , input low voltage 0.4 v max dv dd = 3 v v inh , input high voltage 3.5 v min dv dd = 5 v
AD7794 preliminary technical data rev.pre 6/04 | page 8 parameter AD7794b unit test conditions/comments v inh , input high voltage 2.5 v min dv dd = 3 v input currents 1 a max v in = dv dd or gnd input capacitance 10 pf typ all digital inputs logic outputs (including clk) v oh , output high voltage 2 dv dd C 0.6 v min dv dd = 3 v, i source = 100 a v ol , output low voltage 2 0.4 v max dv dd = 3 v, i sink = 100 a v oh , output high voltage 2 4 v min dv dd = 5 v, i source = 200 a v ol , output low voltage 2 0.4 v max dv dd = 5 v, i sink = 1.6 ma (dout/ rdy )/800 a (clk) floating-state leakage current 1 a max floating-state output capa citance 10 pf typ data output coding offset binary system calibration 2 v max full-scale calibration limit 1.05 x fs v max zero-scale calibration limit -1.05 x fs input span 0.8 x fs v min v min 2.1 x fs v min power requirements 7 power supply voltage av dd C gnd 2.7/5.25 v min/max dv dd C gnd 2.7/5.25 v min/max power supply currents i dd current 150 a max 125 a typ, unbuffered mode, ext. reference 175 a max 150 a typ, buffered mode, in-amp bypassed, ext ref 380 a max 330 a typ, in-amp used, ext. ref 450 a max 400 a typ, in-amp used, int ref i dd (power-down mode) 1 a max 1 temperature range C40c to +105c. 2 specification is not production tested but is supported by characterization data at initial product release. 3 following a self-calibration, this error will be in the order of the noise for the pr ogrammed gain and upda te rate selected. a system calibration will completely remove this error. 4 recalibration at any temperat ure will remove these errors. 5 full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (av dd = 4 v). 6 fs[3:0] are the four bits used in the mode register to select the output word rate. 7 digital inputs equal to dv dd or gnd.
preliminary technical data AD7794 rev.pre 6/04 | page 9 timing characteristics 8, 9 table 2. (av dd = 2.7 v to 5.25 v; dv dd = 2.7 v to 5.25; gnd = 0 v, input logic 0 = 0 v, input logic 1 = dv dd , unless otherwise noted.) parameter limit at t min , t max (b version) unit conditions/comments t 3 100 ns min sclk high pulsewidth t 4 100 ns min sclk low pulsewidth read operation t 1 0 ns min cs falling edge to dout/rdy active time 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 2 10 0 ns min sclk active edge to data valid delay 11 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 5 12, 13 10 ns min bus relinquish time after cs inactive edge 80 ns max t 6 100 ns max sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/rdy high write operation t 8 0 ns min cs falling edge to sclk active edge setup time 11 t 9 30 ns min data valid to sclk edge setup time t 10 25 ns min data valid to sclk edge hold time t 11 0 ns min cs rising edge to sclk edge hold time 8 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.6 v. 9 see figure 2 and figure 3. 10 these numbers are measured with the load circuit of figure 1 and defined as the time requ ired for the output to cross the v ol or v oh limits. 11 sclk active edge is falling edge of sclk. 12 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapol ated back to remove the effects of cha rging or discharging the 50 pf capacitor. t his means that the times quoted in the timing characteristics are the true bus reli nquish times of the part and, as such, ar e independent of external bus loading capa citances. 13 rdy returns high after a read of the adc. in single conversion mode and continuous conversion mode, the same data can be read agai n, if required, while rdy is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. in continuous read mode, the digital word can be read only once.
AD7794 preliminary technical data rev.pre 6/04 | page 10 +1.6 v 50 pf figure 1. load circuit for timing characterization t 2 t 3 t 4 t 1 t 6 t 5 t 7 04227-0-003 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb figure 2. read cycle timing diagram 04227-0-004 i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 figure 3. write cycle timing diagram
preliminary technical data AD7794 rev.pre 6/04 | page 11 absolute maximum ratings table 3. (t a = 25c, unless otherwise noted.) parameter rating av dd to gnd C0.3 v to +7 v dv dd to gnd C0.3 v to +7 v analog input voltage to gnd C0.3 v to av dd + 0.3 v reference input voltage to gnd C0.3 v to av dd + 0.3 v digital input voltage to gnd C0.3 v to av dd + 0.3 v digital output voltage to gnd C0.3 v toa v dd + 0.3 v ain/digital input current 10 ma operating temperature range C40c to +105c storage temperature range C65c to +150c maximum junction temperature 150c tssop ja thermal impedance 97.9c/w jc thermal impedance 14c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD7794 preliminary technical data rev.pre 6/04 | page 12 pin configuration and fu nction descriptions 916 ain2(+) ain5(-)/iout1 10 11 12 15 14 13 ain2(-) ain3(+) ain3(-) ain5(+)/iout2 refin1(-) refin1(+) 520 ain6(+)/p1 gnd 6 7 8 19 18 17 ain6(-)/p2 ain1(+) ain1(-) psw ain4(-)/refin2(-) ain4(+)/refin2(+) 3 4 22 21 cs nc dvdd avdd 1 2 24 23 sclk clk din dout/rdy AD7794 top view (not to scale) figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic function 1 sclk serial clock input for data transfers to and from the adc. the sclk has a schmitt-triggered input, making the interface suitable for opto-isolated applications. the serial clock can be continuous wi th all data transmitted in a continuous train of pulses. alternatively, it can be a noncontinuous clock with the information being trans- mitted to or from the adc in smaller batches of data. 2 clk clock in/clock out. the internal clock can be made availa ble at this pin. alternati vely, the internal clock can be disabled and the adc can be driven by an external clock. this allows several adcs to be driven from a common clock, allowing simultaneous conversions to be performed. 3 cs chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. cs can be hardwired low, allowing the adc to operate in 3-wire mode with sclk, din, and dout used to interface with the device. 4 nc no connect 5 ain6(+)/p1 analog input/digital output pin. ai n6(+) is the positive terminal of the differential analog input pair ain6(+)/ain6(-). alternati vely, this pin can function as a genera l purpose output bit referenced between av dd and gnd 6 ain6(C)/p2 analog input/ digital output pin. ain6(C) is the negative terminal of the differential analog input pair ain6(+)/ain6(-). alternati vely, this pin can function as a genera l purpose output bit referenced between av dd and gnd 7 ain1(+) analog input. ain1 (+) is the positive terminal of the different ial analog input pair ain1(+)/ain1(-). 8 ain1(-) analog input. ain1(C) is th e negative terminal of the differential an alog input pair ain1(+)/ain1(-). 9 ain2(+) analog input. ain2 (+) is the positive terminal of the different ial analog input pair ain2(+)/ain2(-). 10 ain2(-) analog input. ain2(C) is th e negative terminal of the differential an alog input pair ain2(+)/ain2(-). 11 ain3(+) analog input. ain3 (+) is the positive terminal of the different ial analog input pair ain3(+)/ain3(-). 12 ain3(-) analog input. ain3(C) is th e negative terminal of the differential an alog input pair ain3(+)/ain3(-). 13 refin1(+) positive reference input. an external reference can be applied between re fin1(+) and refin1(-). refin1(+) can lie anywhere between v dd and gnd + 0.1 v. the nominal reference voltage (refin1(+) C refin1(C)) is 2.5 v, but the part functions with a reference from 0.1 v to av dd . 14 refin1(-) negative reference in put. this reference input can lie anywhere between gnd and av dd C 0.1 v. 15 ain5(+)/iout2 analog inp ut/output of internal excita tion current source. ain5(+) is the positive terminal of the differe ntial analog input pair ain5(+)/ain5(-). alternatively, the internal excitation current source can be made available at this pin. the excitation current source is programmable so that the current can be 10 ua, 200 ua or 1 ma. either iexc1 or iexc2 can be switched to this output 16 ain5(-)/iout1 analog input/output of in ternal excitation current source.
preliminary technical data AD7794 rev.pre 6/04 | page 13 pin no. mnemonic function ain5(-) is the negative terminal of the differe ntial analog input pair ain5(+)/ain5(-). alternatively, the internal excitation current source can be made available at this pin. the excitation current source is programmable so that the current can be 10 ua, 200 ua or 1 ma. either iexc1 or iexc2 can be switched to this output. 17 ain4(+)/refin2(+) analog inp ut/positive reference input. ain4(+) is the positive terminal of the differe ntial analog input pair ain4(+)/ain4(-). this pin can aso function as a reference in put. refin2(+) can lie anywhere between av dd and gnd + 0.1 v. the nominal reference voltage (refin2(+) C refin2(C)) is 2.5 v, but the part functions with a reference from 0.1 v to av dd . 18 ain4(-)/refin2(-) analog inp ut/negative reference input. ain4(-) is the negative terminal of the differe ntial analog input pair ain4(+)/ain4(-). this pin also functions as the negative reference inp ut for refin2. this reference input can lie anywhere between gnd and av dd C 0.1 v. 19 psw low side power switch to gnd. 20 gnd ground reference point. 21 av dd supply voltage, 2.7 v to 5.25 v. 22 d v dd serial interface supply voltage, 2.7 v to 5.25 v. dv dd is independent of av dd . therefore, the serial interface can be operated at 3 v with av dd at 5 v or vice versa. 23 dout/rdy serial data output/data ready output. dout/rdy serves a dual purpose . it functions as a serial data output pin to access the output shift register of the adc. the outp ut shift register can contain data from any of the on-chip data or control registers. in addition, dout/rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin will go high before the next update occurs. the dout/rdy falling edge can be used as an interrupt to a pr ocessor, indicating that valid data is available. with an external serial clock, the data can be read using the dout/rdy pin. with cs low, the data/control word informa-tion is placed on the dout/rdy pin on the sclk falling edge and is valid on the sclk rising edge. the end of a conversion is also indicated by the rdy bit in the status register. when cs is high, the dout/rdy pin is three-stated but the rdy bit remains active. 24 din serial data input to the inp ut shift register on the adc. data in this shift register is transferred to the control registers within the adc, the register selection bits of the communications register identifying the appropriate register.
AD7794 preliminary technical data rev.pre 6/04 | page 14 typical performance characteristics figure 5. figure 6. figure 7. figure 8. figure 9. figure 10.
preliminary technical data AD7794 rev.pre 6/04 | page 15 on-chip registers the adc is controlled and configured via a number of on-chip registers, which are described on the following pages. in the foll owing descriptions, set implies a logic 1 state and cleared implies a logic 0 state, unless otherwise stated. communications register (rs2, rs1, rs0 = 0, 0, 0) the communications register is an 8-bit write-only register. all communications to the part must start with a write operation t o the com- munications register. the data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. for read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. this is the d efault state of the interface and, on power-up or after a reset, the adc is in this default state waiting for a write operation to the communic ations regis- ter. in situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with din high ret urns the adc to this default state by resetting the entire part. table 5 outlines the bit designations for the communications register. cr0 thr ough cr7 indi- cate the bit location, cr denoting the bits are in the communications register. cr7 denotes the first bit of the data stream. t he number in brackets indicates the power-on/reset default status of that bit. cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 wen (0) r/w (0) rs2(0) rs1(0) rs0(0) cread(0) 0(0) 0(0) table 5. communications register bit designations bit location bit name description cr7 wen write enable bit. a 0 must be written to this bit so that the write to the communications register actually occurs. if a 1 is the first bit written, the part will not cl ock on to subsequent bits in the register. it will stay at this bit location until a 0 is written to this bit. once a 0 is written to the wen bit, the next seven bits will be loaded to the communications register. cr6 r/w a 0 in this bit location indicates that the next operati on will be a write to a specified register. a 1 in this position indicates that the next operation will be a read from the designated register. cr5Ccr3 rs2Crs0 register address bits. these address bits are used to select which of the adcs registers are being selected during this serial interface communication. see table 6. cr2 cread continuous read of the data registe r. when this bit is set to 1 (and th e data register is selected), the serial interface is configured so th at the data register can be continuo usly read, i.e., the contents of the data register are placed on the dout pin automati cally when the sclk pulses are applied. the commu- nications register does not have to be written to fo r data reads. to enable continuous read mode, the instruction 01011100 must be written to the communica tions register. to exit the continuous read mode, the instruction 01011000 must be written to the communications register while the rdy pin is low. while in continuous read mode , the adc monitors activity on the di n line so that it can receive the instruction to exit continuous read mode. additionally, a reset will occur if 32 consecutive 1s are seen on din. therefore, din should be held low in continuous read mode until an instruction is to be written to the device. cr1Ccr0 0 these bits must be programmed to logic 0 for correct operation. table 6. register selection rs2 rs1 rs0 register register size 0 0 0 communications register during a write operation 8-bit 0 0 0 status register during a read operation 8-bit 0 0 1 mode register 16-bit 0 1 0 configuration register 16-bit 0 1 1 data register 24-bit 1 0 0 id register 8-bit 1 0 1 io register 8-bit 1 1 0 offset register 24-bit 1 1 1 full-scaleregister 24-bit
AD7794 preliminary technical data rev.pre 6/04 | page 16 status register (rs2, rs1, rs0 = 0, 0, 0; power-on/reset = 0x88) the status register is an 8-bit read-only register. to access the adc status register, the user must write to the communication s register, select the next operation to be a read, and load bits rs2, rs1 and rs0 with 0. table 7 outlines the bit designations for the st atus register. sr0 through sr7 indicate the bit locations, sr denoting the bits are in the status register. sr7 denotes the first bit of the d ata stream. the number in brackets indicates the power-on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) noref(0) 0(0) 1(1) ch2(0) ch1(0) ch0(0) table 7. status register bit designations bit location bit name description sr7 rdy ready bit for adc. cleared when data is written to th e adc data register. the rdy bit is set automatically after the adc data register has been read or a period of time before the data re gister is updated with a new conversion result to indicate to the user not to read the conversi on data. it is also set when the part is placed in power-down mode. the end of a conversion is indicated by the dout/rdy pin also. this pin can be used as an alternative to the status register for monitori ng the adc for conversion data. sr6 err adc error bit. this bit is written to at the same time as the rdy bit. set to indicate that the result written to the adc data register has been clamped to al l 0s or all 1s. error sources include overrange, underrange or the absence of a reference voltage. cleared by a write operation to start a conversion. sr5 noref no external reference bit. set to indicate that the selected refere nce (refin1 or refin2) is at a voltage that is below a specified threshold. when set , conversion results are clamped to all ones. cleared to indicate that a valid reference is applied to the selected reference pins. the noxref bit is enabled by setting the ref_det bit in the configuration register to 1. the err bit is also set if the voltage applied to the selected reference input is invalid. sr4 0 this bit is automatically cleared . sr3 1 this bit is automatically set . sr2Csr0 ch2Cch0 these bits indicate which channel is being converted by the adc. mode register (rs2, rs1, rs0 = 0, 0, 1; power-on/reset = 0x000a) the mode register is a 16-bit register from which data can be read or to which data can be written. this register is used to se lect the oper- ating mode, the update rate and the clock source. table 8 outlines the bit designations for the mode register. mr0 through mr15 indicate the bit locations, mr denoting the bits are in the mode register. mr15 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. any write to the setup register resets the modulator and filter and se ts the rdy bit. mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 md2(0) md1(0) md0(0) psw(0) 0(0) 0(0) 0(0) 0(0) mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 clk1(0) clk0(0) 0(0) chop-dis (0) fs3(1) fs2(0) fs1(1) fs0(0) table 8. mode register bit designations bit location bit name description mr15Cmr13 md2Cmd0 mode select bits. these bits select th e operational mode of the AD7794 (see table 9). mr12 psw power switch control bit. set by user to close the power switch psw to gnd. the power switch can sink up to 20 ma. cleared by user to open the power switch. when the adc is placed in power-down mode, the power switch is opened. mr11-mr8 0 these bits must be programm ed with a logic 0 for correct operation. mr7-mr6 clk1-clk0 these bits are used to select the clock source fo r the AD7794. either the on-chip 64 khz clock can be used or an external clock can be us ed. the ability to use an external clock is useful as it allows several AD7794 devices to be synchronised. also, 50 hz/60 hz rejection is improved when an accurate external clock drives the AD7794.
preliminary technical data AD7794 rev.pre 6/04 | page 17 bit location bit name description clk1 clk0 adc clock source 0 0 internal 64 khz clock, internal clock is not available at the clk pin 0 1 internal 64 khz clock. this clock is made available at the clk pin 1 0 external 64 khz clock used. the exte rnal clock can have a 45:55 duty cycle. 1 1 external clock used. this external clock is divided by 2 within the AD7794. this allows the user to supply a clock which has a duty cycle worse than a 45:55 duty cycle to the AD7794, for example, a 128 khz clock. mr5 0 this bit must be programmed with a logic 0 for correct operation. mr4 chop-dis this bit is used to enable or disable chopping. on power-up or following a reset, chop-dis is cleared so chopping is enabled. when chop-dis is set, chopping is disabled. mr3-mr0 fs3-fs0 filter update rate select bits (see table 10). table 9. operating modes md2 md1 md0 mode 0 0 0 continuous conversion mode (default). in continuous conversion mo de, the adc continuously performs conversi ons and places the result in the data register. rdy goes low when a conversion is complete. the user can read these conversions by placing the device in continuous read mode whereby the conversi ons are automatically placed on the dout line when sclk pulses are applied. alternatively, the user can inst ruct the adc to output the conversion by writing to the communications register. after power-on, the firs t conversion is available after a period 2/ f adc when chopping is enabled or 1/ f adc when chopping is disabled. subseq uent conversions are available at a frequency of f adc with chopping either enabled or disabled, 0 0 1 single conversion mode. in single conversion mode, the adc is placed in power-down mode when conversions are not being performed. when single conversion mode is selected, the adc powers up and performs a single conversion, which occurs after a period 2/f adc when chopping is enabled or 1/ f adc when chopping is disabled. the conversion result in placed in the data register, rdy goes low, and the adc returns to power-down mode. the conversion remains in the data register and rdy remains active (low) until the data is read or another conversion is performed. 0 1 0 idle mode. in idle mode, the adc filter and modulator are held in a reset state although the modulator clocks are still provided 0 1 1 power-down mode. in power down mode, all the AD7794 circuitry is powered down including the current sources, power switch, burnout currents, bias voltage generator and clkout circuitry. 1 0 0 internal zero-scale calibration. an internal short is automa tically connected to the enabled channel. a calibration takes 2 conversion cycles to complete when chopping is enabled and 1 co nversion cycle when chopping is disabled. rdy goes high when the calibration is initiated and returns low when th e calibration is complete. the adc is placed in idle mode following a calibration. the meas ured offset coefficient is placed in the offset register of the selected channel 1 0 1 internal full-scale calibration. the fullscale input voltage is automatically connected to the selected analog input for this calibration. the full-scale error of the AD7794 is calbrated at a gain of 1 using the internal refere nce in the factory. when a channel is operated with a gain of 1 and the internal reference is selected, this factory-calibrated value is loaded into the full-scale register when a full-scale calibration is initiated. when an external reference is selected at a gain of 1, an internal fullscale calibration can be performed. when the gain equals 1, a calibration takes 2 conversion cycles to complete when chopping is enabled and 1 conversion cycle when chopping is disabled. for higher gains, 4 conversion cycles are required to perform the fullscale calibration when chopping is enabled and 2 conversion cycles when chopping is disabled. rdy goes high when the calibration is initiated and returns low when the ca libration is complete. the adc is placed in idle mode following a calibration. the measured fullscale coefficient is placed in the fullscale register of the selected channel. internal full-scale calibrations cannot be performed wh en the gain equals 128. with this gain setting, a system full-scale calibration can be performed.
AD7794 preliminary technical data rev.pre 6/04 | page 18 a fullscale calibration is required each time the gain of a channel is changed. 1 1 0 system offset calibration. user should connect the system zero-s cale input to the .channel input pins as selected by the ch2-ch0 bits. a system offset calibration takes 2 conversion cycl es to complete when chopping is enabled and one conversion cycle when chopping is disabled. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured offset coefficient is placed in the offset register of the selected channel. 1 1 1 system full-scale calibration. user should connect the system full-scale input to the .channel input pins as selected by the ch2-ch0 bits. a calibration takes 2 conversion cycles to complete when chopping is enabled and one conversion cycle when chopping is disabled.. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured fullscale coefficient is placed in the fullscale register of the selected channel. a fullscale calibration is required each time the gain of a channel is changed. table 10. update rates available (chopping enabled) fs3 fs2 fs1 fs0 f adc (hz) tsettle (ms) rejection@ 50 hz / 60 hz (internal clock) 0 0 0 0 x x 0 0 0 1 500 5 0 0 1 0 250 8 0 0 1 1 125 16 0 1 0 0 62.5 32 0 1 0 1 50 40 0 1 1 0 41.6 48 0 1 1 1 33.3 60 1 0 0 0 19.6 101 90 db (60 hz only) 1 0 0 1 16.6 120 84 db (50 hz only) 1 0 1 0 16.6 120 70 db (50 hz and 60 hz) 1 0 1 1 12.5 160 67 db (50 hz and 60 hz) 1 1 0 0 10 200 69 db (50 hz and 60 hz) 1 1 0 1 8.33 240 73 db (50 hz and 60 hz) 1 1 1 0 6.25 320 74 db (50 hz and 60 hz) 1 1 1 1 4.17 480 79 db (50 hz and 60 hz) with chopping disabled, the update rates remain unchanged but the settling time for each update rate is reduced by a factor of 2. the rejection at 50 hz/60 hz for a 16.6 hz update rate degrades to 60 db. configuration register (rs2, rs1, rs0 = 0, 1, 0; power-on/reset = 0x0710) the configuration register is a 16-bit register from which data can be read or to which data can be written. this register is u sed to configure the adc for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain and select the ana- log input channel. table 11 outlines the bit designations for the filter register. con0 through con15 indicate the bit location s, con denoting the bits are in the configuration register. con15 denotes the first bit of the data stream. the number in brackets ind icates the power-on/reset default status of that bit. con15 con14 con13 con12 co n11 con10 con9 con8 vbias1(0) vbias0(0) bo(0) u/b (0) 0(0) g2(1) g1(1) g0(1) con7 con6 con5 con4 con3 con2 con1 con0 refsel1(0) refsel0(0) ref_det(0) buf(1) ch3(0) ch2(0) ch1(0) ch0(0)
preliminary technical data AD7794 rev.pre 6/04 | page 19 table 11. configuration register bit designations bit location bit name description con15C con14 0 bias voltage generator enable. the negative terminal of the analog inputs can b e biased up to vdd/2. vbias1 vbias0 bias voltage 0 0 bias voltage generator disabled 0 1 bias voltage generato r connected to ain1(-) 1 0 bias voltage generato r connected to ain2(-) 1 1 bias voltage generato r connected to ain3(-) con13 bo this bit must be programmed with a logic 0 for correct operation. burnout current enable bit. when this bit is set to 1 by the user, the 100 na current sources in the signal path are enabled. when bo = 0, the burnout curren ts are disabled. the burnout currents can be enabled only when the buffer or in-amp is active. con12 u/b unipolar/bipolar bit. set by user to enable unipolar coding, i.e., zero differential input will result in 0x000000 output and a full-scale differentia l input will result in 0xffffff output. cleared by the user to enable bipolar coding. negative full-scale differential input will result in an output code of 0x000000, zero differential input will result in an output co de of 0x800000, and a positive full-scale differential input will result in an output code of 0xffffff. con11 0 this bit must be programmed with a logic 0 for correct operation. con10- con8 g2-g0 gain select bits. written by the user to select the adc input range as follows g2 g1 g0 gain adc input range (2.5v reference) 0 0 0 1 (in-amp not used) 2.5 v 0 0 1 2 (in-amp not used) 1.25 v 0 1 0 4 625 mv 0 1 1 8 312.5 mv 1 0 0 16 156.2 mv 1 0 1 32 78.125 mv 1 1 0 64 39.06 mv 1 1 1 128 19.53 mv con7- con6 refsel1/refsel0 reference select bits. the referenc e source for the adc is selected using these bits. refsel1 refsel0 reference source 0 0 external reference applied between refin1(+) and refin1(-) 0 1 external reference applied between refin2(+) and refin2(-) 1 0 internal 1.17 v reference 1 1 reserved con5 ref_det enables the reference detect function. when set , the noxref bit in the status re gister indicates when the external reference being used by the adc is open circuit or less than 0.5 v. when cleared , the reference detect function is disabled. con4 buf configures the adc for buffered or unbuffered mode of operation. if cleared , the adc operates in unbuffered mode, lowering the power consumption of the device. if set , the adc operates in buffered mode, allowing the user to place source impedances on the front end without co ntributing gain errors to the system. for gains of 1 and 2, the buffer can be enabled or disabled. for higher gains, the buffer is automatically enabled. con3- con0 ch3-ch0 channel select bits. written by the user to select the ac tive analog input channel to the adc. ch3 ch2 ch1 ch0 channel calibration pair 0 0 0 0 ain1(+) C ain1(-) 0 0 0 0 1 ain2(+) C ain2(-) 1 0 0 1 0 ain3(+) C ain3(-) 2 0 0 1 1 ain4(+) C ain4(-) 3
AD7794 preliminary technical data rev.pre 6/04 | page 20 bit location bit name description 0 1 0 0 ain5(+) C ain5(-) 3 0 1 0 1 ain6(+) C ain6(-) 3 0 1 1 0 temp sensor automatically selects the internal reference and sets the gain to 1 0 1 1 1 vdd monitor automatically selects the internal 1.17 v reference and sets the gain to 1/6 1 0 0 0 ain1(-) C ain1(-) 0 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved data register (rs2, rs1, rs0 = 0, 1, 1; power-on/reset = 0x000000) the conversion result from the adc is stored in this data register. this is a read-onl y register. on completion of a read opera tion from this register, the rdy bit/pin is set. id register (rs2, rs1, rs0 = 1, 0, 0; power-on/reset = 0xxf) the identification number for the AD7794 is stored in the id register . this is a read-only register. io register (rs2, rs1, rs0 = 1, 0, 1; power-on/reset = 0x00) the i/o register is an 8-bit register from which data can be read or to which data can be written. this register is used to ena ble the excitation currents and select the value of the excitation currents. table 12 outlines the bit designations for the io register. io0 throu gh io7 indicate the bit locations, io denoting the bits are in the io register. io7 denotes the first bit of the data stream. the number in bra ckets indicates the power-on/reset default status of that bit. io7 io6 io5 io4 io3 io2 io1 io0 0(0) ioen(0) io2dat(0) io1dat(0) iexc dir1(0) iexcdir0(0) iexcen1(0) iexcen0(0) table 12 filter register bit designations bit location bit name description io7 0 this bit must be programmed with a logic 0 for correct operation. io6 ioen configures the pins ai n6(+)/p2 and ain6(-)/p2 are analog input pins or digital output pins. when this bit is set , the pins are configured as digital output pins p1 and p2. when this bit is cleared , these pins are configured as anal og input pins ain6(+) and ain6(-). io5-io4 io2dat/io1dat p2/p1 data. when ioen is set, the data for th e digital output pins p1 and p2 is written to bits io2dat and io1dat. io3-io2 iexcdir1C iexcdir0 direction of current sources select bits. iexcdir1 iexcdir0 current source direction 0 0 current source iexc1 connected to pin iout1, current source iexc2 connected to pin iout2 0 1 current source iexc1 connected to pin iout2, current source iexc2 connected to pin iout1 1 0 both current sources connected to pi n iout1. permitted only when the current sources are set to 10 ua or 200 ua 1 1 both current sources connected to pi n iout2. permitted only when the current sources are set to 10 ua or 200 ua io3-io2 iexcen1C these bits are used to enab le and disable the current sources along with selecting the value of the
preliminary technical data AD7794 rev.pre 6/04 | page 21 bit location bit name description iexcen0 excitation currents. iexcen1 iexcen0 current source value 0 0 excitation currents disabled 0 1 10 ua 1 0 200 ua 1 1 1 ma offset register (rs2, rs1, rs0 = 1, 1, 0; power-on/reset = 0x800000) the offset register holds the offset calibration coefficient for the adc. the power-on-reset value of the internal zero-scale c alibration coefficient register is 800000 hex. the AD7794 has 4 offset registers. channels ain1 to ain3 have dedicated offset registers wh ile chan- nels ain4, ain5 and ain6 share an offset register. each of these registers is a 24-bit read/write register. this register is used in conjunction with its associated full-scale register to form a register pair. the power-on-reset value is automatically overwri tten if an in- ternal or system zero-scale calibration is initiated by the user . the AD7794 must be placed in power down mode or idle mode wh en writing to the offset register. full-scale register (rs2, rs1, rs0 = 1, 1, 1; power-on/reset = 0x5xxxx5) the full-scale registers is a 24- bit register that holds the full-scale calibrat ion coefficient for the adc. the ad77794 has 4 full-scale registers. channels ain1, ain2 and ain3 have dedicated full-scale registers while channels ain4, ain5 and ain6 share a registe r. the full-scale registers are read/write registers. however, when wr iting to the full-scale registers, the adc must be placed in po wer down mode or idle mode. these registers are configured on power-on with factory-calibrated internal full-scale calibration coeffici ents, the factory calibration being performed with the gain set to 1 and us ing the internal reference. therefore, every device will have different default coefficients. these default values are used when the device is operated with a gain of 1 and when the internal referenc e is selected. for other gains or when the external reference is used at a gain of 1, these default coefficients will be automatically overwri tten if an internal or system full-scale calibration is initiated by the us er. a full-scale calibration should be performed when the gain is changed. typical application (flowmeter) gnd avdd AD7794 serial interface and control logic internal clock clk sigma delta adc in-amp dout/rdy din sclk cs dvdd ain1(+) ain1(-) v dd gnd v dd psw gnd ain3(+) ain2(+) ain2(-) in+ in- out+ out- in+ in- out+ out- vdd refin1(+) refin1(-) ain3(-) mux r cm iout1

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